1 Background 2 Introduction to OpenCL for FPGA
3 FPGA Accelerator Design Using OpenCL
4 FPGA-Oriented Parallel Programming
5 Exploiting the Memory Hierarchy
6 Design Examples
Index
About the Author:

Waidyasoriya Hasitha Muthumala is an Assistant Professor in the Graduate School of Information Sciences at Tohoku University. He received the BE degree in information engineering, the MS degree in information sciences, and the PhD degree in information sciences from Tohoku University, Japan, in 2006, 2008, and 2010 respectively. His research interests include reconfigurable computing, processor architectures for big-data applications, and high-level design methodology for VLSIs. He is a member of the IEEE.

Masanori Hariyama is a Professor in the Graduate School of Information Sciences at Tohoku University. He received the BE degree in electronic engineering, the MS degree in information sciences, and the PhD degree in information sciences from Tohoku University, Japan, in 1992, 1994, and 1997, respectively. His research interests include real-world applications such as robotics and medical applications, big data applications such as bio-informatics, high-performance computing, VLSI computing for real-world application, high-level design methodology for VLSIs, and reconfigurable computing. He is a member of the IEEE.

Kunio Uchiyama, technical advisor of Hitachi, Ltd., received his BS, MS, and PhD degrees from the Tokyo Institute of Technology. He has worked for the Central Research Laboratory of Hitachi since 1978 on design automation, mainframe computers, microprocessors, multicore processors, and their applications. He led R&D for the commercial SuperH microprocessors from the early 1990s, and he was awarded Japan's national Medal of Honor with the Purple Ribbon in 2004 for his contribution to the development of commercial high-performance, low-power microprocessors. He also led the New Energy and Industrial Technology Development Organization project in Japan on heterogeneous multicore technologies from 2007 to 2010. He was a guest editor of IEEE Micro in 2005 and served as a general chair of the Asia and South Pacific Design Automation Conference sponsored by IEEE CAS/CEDA in 2015. He has also been a vice chair of the IEEE Symposium on Low-Power and High-Speed Chips, sponsored by the IEEE Computer Society since 2008. He is a member of the IEEE Computer Society, Solid-State Circuits Society, and the Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE and IEICE, and is a member of Board of Governors of IEEE Computer Society.