List of Contributors. Preface. 1. Introduction. 1.1 Why SOI? 1.2 What is SOI? -Structure -. 1.3 Advantages of SOI. 1.4 History of the Development of SOI Technology. 1.5 Partially-Depleted (PD) and Fully-Depleted (FD) SOI . MOSFETs, and Future MOSFETs. 1.6 Summary. References. 2. FD-SOI Device and Process Technologies. 2.1 Introduction. 2.2 FD-SOI Devices. 2.3 Theoretical Basis of FD-SOI Device Operation: DC Operation. 2.4 FD-SOI CMOS Process Technology. 2.5 Summary. References 3. Ultralow-Power Circuit Design with FD-SOI Devices. 3.1 Introduction. 3.2 Ultralow-Power Short-Range Wireless Systems. 3.3 Key Design Factor for Ultralow-Power LSIs. 3.4 Ultralow-Voltage Digital-Circuit Design. 3.5 Robustness of Ultralow-Voltage Operation. 3.6 Prospects and Issues in Low-Voltage Analog Circuits. 3.7 Technology Scaling, Analog Performance, and Performance Trend for Electrical Systems. 3.8 Low-Voltage Analog Circuit. 3.9 Fully-Depleted SOI Devices for Ultralow-Power Analog Circuits. 3.10 Future Direction of RF and Mixed Signal Systems. 3.11 Summary. References. 4. 0.5-V MTCMOS/SOI Digital Circuits. 4.1 Introduction. 4.2 MTCMOS/SOI Circuits. 4.3 Adder. 4.4 Multiplier. 4.5 Memory. 4.6 Frequency Divider. 4.7 CPU. 4.8 Summary. References. 5. 0.5-1V MTCMOS/SOI Analog/RF Circuits. 5.1 Introduction. 5.2 RF Building Blocks. 5.3 AD and DA Converters. 5.4 DC-DC Converter. 5.5 I/O and ESD-Protection Circuitry for Ultralow-Power LSIs. 5.6 Summary. References 6. SPICE Model for SOI MOSFETs. 6.1 Introduction. 6.2 SPICE Model for SOI MOSFETs. 6.3 Parameter Extraction. 6.4 Example of SOI MOSFET Simulation. 6.5 Summary. References. 7. Applications. 7.1 Introduction. 7.2 1-V Bluetooth RF Transceiver and Receiver. 7.3 Solar-Powered, Radio-Controlled Watch. 7.4 Batteryless Short-Range Wireless System. 7.5 Summary. References. 8.Prospects for FD-SOI Technology. 8.1 Introduction. 8.2 Evolution of Nanoscale FD-SOI Devices. 8.3 Device and Substrate Technologies for Ultrathin-Body SOI MOSFETs. 8.4 Power-Aware Electronics and Role of FD-SOI Technology. 8.5 Summary. References.
About the Author:

Takayasu Sakurai received the Ph.D degree in Electronic Engineering from University of Tokyo, Japan, in 1981 and he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, BiCMOS ASIC's, RISC's, and multimedia VLSI's. He worked on simple yet accurate interconnect delay, capacitance and MOS models widely used as alpha power-law MOS model. He proposed to sense-amplifying flip-flops, variable threshold voltage CMOS scheme, dual voltage converter scheme, hot carrier resilient circuits and other numerous digital and memory circuits, which are adopted in current high-performance, low-power VLSI's. He was a visiting researcher at University of California, Berkeley from 1988 to 1990. In 1996, he moved to University of Tokyo and is consulting to US startup companies. He has published about 250 technical publications including more than 30 invited papers and 6 books and filed about 100 patents. He is a recipient of four product awards and two design contest awards. He served as a conference chair for the Symposium on VLSI Circuits, and a technical program committee member for ISSCC, CICC, DAC, ICCAD, FPGA workshop, ISLPED, ASPDAC, TAU, and other international conferences. He is a keynote speaker for the 2003 ISSCC. He is an IEEE Fellow, an elected Administration Committee member for the IEEE Solid-State Circuits Society and an IEEE CAS distinguished lecturer.