Abstract Contents List of Tables List of Figures Symbols and Abbreviations Physical Definitions 1 Introduction 1.1 Motivation 1.2 Outline of the work 2 ADCs in Deep-Submicron CMOS Technologies 2.1 Introduction 2.2 Scaling-Down of CMOS Technologies 2.2.1 Driving Force of the CMOS Scaling-Down 2.2.2 Moving Into Deep-Submicron CMOS Technologies 2.3 Impact of Moving Into Deep-Submicron CMOS to Analog Circuits 2.3.1 Decreased Supply Voltage 2.3.2 Impact on Transistor Intrinsic Gain 2.3.3 Impact on Device Matching 2.3.4 Impact on Device Noise 2.4 ADCs In Deep-Submicron CMOS 2.4.1 Decreased Signal Swing 2.4.2 Degraded Transistor Characteristics 2.4.3 Distortion 2.4.4 Switch Driving 2.4.5 Improved Device Matching 2.4.6 Digital Circuits Advantages 2.5 Conclusion 3 Principle of sigma-delta ADC 3.1 Introduction 3.2 Basic Analog to Digital Conversion 3.3 Oversampling and Noise Shaping 3.3.1 Oversampling 3.3.2 Noise Shaping 3.3.3 sigma-delta modulator 3.3.4 PerformanceMetrics for the sigma-delta ADC 3.4 Traditional sigma-delta ADC Topology 3.4.1 Single-Loop Single-Bit sigma-delta Modulators 3.4.2 Single-Loop Multibit sigma-delta Modulators 3.4.3 Cascaded sigma-delta Modulators 3.5 Conclusion 4 Low-Power Low-Voltage sigma-delta ADC Design in Deep-Submicron CMOS: Circuit Level Approach 4.1 Introduction 4.2 Low-Voltage Low-Power OTA Design 4.2.1 Gain Enhanced Current Mirror OTA Design 4.2.2 A Test Gain-Enhanced Current Mirror OTA 4.2.3 Implementation and Measurement Results 4.2.4 Two-Stage OTA Design 4.3 Low-Voltage Low-Power sigma-delta ADC Design 4.3.1 Impact of Circuit Nonidealities to sigma-delta ADC Performance 4.3.2 Modulator Topology Selection 4.3.3 OTA Topology Selection 4.3.4 Transistor Biasing 4.3.5 Scaling of Integrators 4.4 A 1-V 140-µWsigma-delta modulator in 90-nm CMOS 4.4.1 Building Block Circuits Design 4.4.2 Implementation 4.4.3 Measurement Results 4.5 Measurements on PSRR and Low-Frequency Noise Floor 4.5.1 Introduction of PSRR 4.5.2 PSRR Measurement Setup 4.5.3 PSRR Measurement Results 4.5.4 Measurement on Low-Frequency Noise Floor 4.6 Conclusion 5 Low-Power Low-Voltage sigma-delta ADC Design in Deep-Submicron CMOS: System Level Approach 5.1 Introduction 5.2 The Full Feedforward sigma-delta ADC Topology 5.2.1 Single-Loop Single-Bit Full Feedforward sigma-delta Modulators 5.2.2 Single-Loop Multibit Full Feedforward sigma-delta Modulators 5.2.3 Cascaded Full Feedforward sigma-delta Modulators 5.3 Linearity Analysis of sigma-delta ADC 5.3.1 Non-LinearitiesModeling in sigma-delta ADC 5.3.2 Non-Linear OTA Gain Modeling in sigma-delta ADC 5.3.3 Linearity Performance Comparison 5.4 Circuit Implementation of the Full Feedforward sigma-delta Modulator 5.5 A 1.8-V 2-MS/s sigma-delta Modulator in 0.18-µm CMOS 5.5.1 Implementation 5.5.2 Measurement results 5.6 A 1-V 1-MS/s sigma-delta Modulator in 0.13-µm CMOS 5.6.1 Implementation 5.6.2 Measurement Results 5.7 Multibit Full Feedforward sigma-delta Modulator Design 5.7.1 Optimized Loop Coefficients 5.7.2 Circuit Implementation 5.8 Conclusion 6 Flash ADC Design in Deep-Submicron CMOS 6.1 Introduction 6.2 Mismatch Study in Deep-Submicron CMOS Technologies 6.2.1 Mismatch of Components
About the Author: Prof. Michiel Steyaert received his Ph.D. degree in electronics from the Katholieke Universiteit Leuven (KUL) in June 1987. In 1988 he was an associated assistant professor at the U.C.L.A. From 1989 he joined the ESAT-MICAS group at the KUL, were he is now a Full Professor. His current research interests are in analog integrated circuits for high-frequency telecommunication systems and high performance analog signal processing. He authored or co-authored over 250 papers and co-authored over 5 books. He received the 1990 European Solid-State Circuits Conference Best Paper Award, the 1995 and 1997 ISSCC Evening Session Award, the 1999 IEEE Circuit and Systems Society Guillemin-Cauer Award and the 1991 NFWO Alcatel-Bell-Telephone award for innovative work in integrated circuits for telecommunications.