Preface. Acknowledgments. 1 Introduction. 2 Design Flow Overview. 2.1 Design Levels. 2.2 Top-down System Design. 2.3 Bottom-up Verification. 3 Simulation Tools in System Design. 3.1 Use of Simulation Tools within the Design Flow. 3.2 Specific Simulation Algorithms of RF Simulators. 3.3 Criteria of the Simulator Selection. 3.4 Internet Resources for Simulation Tools. 4 System Level Modeling. 4.1 System Level Simulation. 4.2 Simulation Technology of System Level Simulators. 4.3 Complex Baseband Simulation. 4.4 Model Libraries for System Simulation. 4.5 Creation of Own Primitive and Hierarchical Models. 5 VHDL-AMS for Block Level Simulation. 5.1 Introduction. 5.2 VHDL-AMS Standardization. 5.3 A Simple Block Level Example - Analog PLL. 5.4 Summary 6 Introduction to VHDL-AMS. 6.1 Aim of this Introduction. 6.2 Repetition of Basics of VHDL 1076-1993. 6.3 Conservative Systems Description. 6.4 Description of Nonconservative Systems. 6.5 Mixed-Signal Simulation. 6.6 Analysis Domains. 6.7 Summary. 7 Selected RF Blocks in VHDL-AMS. 7.1 Library Overview. 7.2 Signal Sources. 7.3 Basic RF Building Blocks. 7.4 Measurement and Observation Units. 7.5 Block Level Example of a Linear PLL. 8 Macromodeling in VHDL-AMS. 8.1 Introduction. 8.2 General Methodology. 8.3 Input and Output Stages. 8.3.1 Input stages. 8.3.2 Output stages. 8.4 OpAmp Macromodel. 9 Complex Example: WLAN Receiver. 9.1 Introduction. 9.2 Example Specification. 9.3 Example Modeling. 9.4 Example Calibration. 9.5 Example Verification. 10 Modeling of Analog Blocks in Verilog-A. 10.1 Introduction. 10.2 Writing Custom Behavioral Models. 10.3 Overview of the Cadence Model Library rfLib. 10.4 Modeling and Simulation of a WLAN Receiver. 11 Characterization forBottom-Up Verification. 11.1 Concept of Characterization. 11.2 RF Characteristics and Parameters. 11.3 Application of Characterization. 11.4 Example Characterization of an LNA. 11.5 Characterization Environment. 11.6 Characterization Using the OCEAN Script Language. 12 Advanced Methods for Overall System Specification and Validation. 12.1 Gap between System Level and Block Level Simulation. 12.2 File Coupling of Simulators. 12.3 Direct Cosimulation of System Level and Analog Simulators. 12.4 Generated Black Box Models. References. Index.