Molecular Electronics Materials, Devices and Applications

List of Figures. List of Tables. Part I General introduction Part II State of the Art 1. MOLECULAR ELECTRONICS MATERIALS. 1 Nanowires. 2 Molecular-gated semiconductor nanowire transistor. 3 Carbon nanotubes. 4 Nanotechnology and molecules. 2. MOLECULAR ELECTRONIC ARCHITECTURES. 1 Short overview on Artificial Neural Network. 2 Nanocell: The bottom-up approach. 3 Nanofabric: A programmable and defct-tolerant architecture. 4 Nanoscale FPGA 5 Micro-nano interface. 6 Neuromorphic architecture. 7 Molecular realization of Quantum Cellular Automata. 8 The molecular crossbar. 3. NON-VOLATILE MEMORY CELLS. 1 Short introduction. 2 Conventional non-volatile memory cells. 3 NAND and OR architectures. 4 Emerging non-volatile memories. 5 Memory cell based on nanotechnology. Part III Case study 4. MODELING OF THE MOLECULAR NWFET TRANSISTOR. 1 VHDL-AMS. 2 Modeling. 3 Simulation. 5. PRESENTATION OF THE MOLECULAR MEMORY CELL. 1 The molecular memory cell. 2 The simple memory cell. 3 Speed optimized modeling of the memory cell. 4 Conclusion and perspectives. 6. TECHNOLOGICAL DISPERSIONS TOLERANT ARCHITECTURES. 1 Architecture generation tool. 2 Architectures. 3 Conclusion and perspectives. Appendices. A Simulation results. 1 Raw data for method Reference. 2 Raw data for method Error Sensing. 3 Raw data for method Loop Error Sensing. 4 Raw data for method ECC H4/3b. 5 Raw data for method ECC H5/4b. 6 Raw data for method ECC H5/3b. B VHDL-AMS code examples. 1 VHDL-AMS source code of themodeling of amolecular-gated semiconductor nanowire transistor. 2 VHDL-AMS source code of themodeling of amolecular-gated semiconductor nanowire transistor. 3 VHDL-AMS source code example of a ECC memory state machine (H5/3b). 4 VHDL-AMS source code example: MyPackageH5/3b. References. Index.
About the Author:

Antoine Jalabert received in 2003 the Eng. Diploma, the M.Sc. Degree in Electrical Eng. from the Ecole Supérieure d'Electronique de l'Ouest (ESEO), Angers, FR, after joining one year the Institut Supérieur d'Electronique de Paris (ISEP), Paris, FR, where he specialized in microelectronics and System on Chip (SoC). In 2003, he also worked for 10 months in Prof. De Micheli's group at Standford University where he contribuited to the development of XPipesCompiler, an EDA tool for non-regular Network on Chip (NoC) topology fine-tuned implementation.
He then moved to Grenoble where he obtained in 2006 his Ph.D. degree with the Lab. d'Electronique, de Technologie et d'Instrumentation (LETI), MINATEC-CEA-Grenoble, FR, and ISEP-ENST in Paris, FR for his work on fault-tolerant computing and memory architectures using molecular electronics and nanotechnology modelling ("Post-CMOS Molecular 200mm" / "Chimtronic" projects).
In the late 2006, Antoine joined Infineon Technologies Austria AG main Automotive competence center in Villach, Austria, where he is currently working as a Concept Engineer, focusing on robust design for critical automotive safety application.

Prof. Amara Amara got his Ph.D. in computer science in 1989 and a Master in 1984 in microelectronics and computer science both from Paris VI University (Jussieu). From 1989 to 1992, he was assistant professor developing microelectronics academic programs for the Microelectronic Center of Paris Iles-de-France and took part actively to European Research Projects. In 1992, he joined ISEP (Paris Institute for Electronics) in charge of the microelectronics laboratory where he headed a team involved in High Speed GaAs VLSI circuit design. His current position is Deputy Managing Director in charge of Research and International Cooperation. His research interests are mainly focusing on Low Power circuit design techniques, Design and Technology Interaction for advanced technologies and Robust circuits design. In 1999, he did a sabbatical at Stanford University where he joined Prof. De Micheli's group.
Amara is Member of IEEE Circuit And Systems Board of Governors, General Vice President of the France IEEE Section since Jan. 2008. From 2000 to 2004 he was Chairman of the IEEE-CAS France Chapter (Recipient of the 2004 Best Chapter of the Year Award and a Certificate of Appreciation from IEEE Regional Activities) and is currently counselor of the IEEE student branch at ISEP. He is member of the French CEA (Atomic Energy Agency) Scientific Committee, member of numerous Conference Technical Program Committees and Conference Organizing Committees and member of the Editorial Board of MicroElectronics Journal. Amara is the General Chair of ISCAS 2010 in Paris.
Amara published numerous papers in international conferences and journals and is currently adviser of many PhD students.

Fabien Clermidy obtained his Masters degree in 1994 and his Ph.D in Eng. Science in 1999 on fault-tolerant architectures. He then started working at the Center for Atomic Energy (CEA) in Saclay (near Paris) in 2000 as a research engineer. In this position, he participated in the design of a massively parallel and reconfigurable computer, with fault-tolerant features.
He then moved to Grenoble and became the main architect of the Network-on-Chip activity at the microelectronic laboratory of CEA. He is currently a project leader in the development of complex chips for advanced telecommunication protocols applications. He is also a main contributor in the development of molecular electronic architectures inside the CEA internal "chemtronic" project, involving chemists, physicists, technologists and system architect designers to build future computing architectures.
Fabien Clermidy has published more than 20 papers in international conferences and journals including ISSCC, Symposium on VLSI circuits and JSSC, and is the main inventor or co-inventor of 7 patents.