Next-Generation High-Speed Satellite Interconnect

About the Book

Introduction to satellite On board data-handling.- The SpaceFibre standard.- Building Blocks of a SpaceFibre Network: Example designs.- Interoperability test: how to verify Compliance to the Standard.- Set-up and Characterisation of a SpaceFibre Network.- Survey on Existing and Future SpaceFibre - based solutions.- Conclusions.

About the Author: Pietro Nannipieri graduated cum Laude in Electronic Engineering (MSc) at the University of Pisa in June 2016 and got his PhD from University of Pisa in 2020 cum laude. During his bachelor's degree, he has been a visiting student at University College of London for one year. His interests are digital and VLSI design as well as electronics for space applications. He took part in the 18th and 21st ESA Rexus Program with PHOS team as an electronic engineer and with U-PHOS Team as the project manager. Pietro spent several Months in 2019 as Visiting Researcher in the TEC-EDP Section in ESTEC (ESA), where he carried out different qualification test on the SpaceFibre technology and participated actively to several SpaceWire/SpaceFibre working group. He is currently a Post-doc researcher in the VLSI lab of the information engineering department, University of Pisa. His work mainly focuses on the development of IPs for satellite onboard data handling, (i.e. SpaceFibre), but also signal processing and Hardware-Cyber-security.

Gianmarco Dinelli received the M.Sc. degree in Electronic Engineering cum Laude from the University of Pisa. He is a PhD candidate of the VLSI lab pf the Department of Information Engineering of Pisa University. His work is mainly related to digital system design, from system specifications to hardware implementation on an FPGA device. His research interests are mainly focused on satellite data-handling subsystem and on FPGA-based hardware accelerators for machine learning on the edge applications.

Luca Dello Sterpaio graduated from the University of Pisa, where he achieved his Master of Science degree in Electronic Engineering in June 2016. After four months as Research Fellow at Dept. of Information Engineering, he enrolled in the University of Pisa PhD program. His research activity is mainly focused on the hardware and software digital design for communications in the aerospace field of applications. He is currently the manager of SpaceFibre based technology at IngeniArs S.r.l. Luca is also a Certified LabVIEW Developer (CLD).

Antonino Marino received the M.Sc. degree in Electronic Engineering from University of Pisa in May of 2016 with a thesis on design and verification of test-equipment for SpaceFibre standard. He is a PhD candidate in the VLSI lab of the Information Department, University of Pisa. He has gained valuable experience on the State-of-the-Art spacecraft's onboard communication standard such as SpaceWire and SpaceFibre. He has considerable experiences in Embedded System development and HW/SW co-design flow. His research interests are focused on the development of innovative test equipment for spacecraft onboard communication protocol and in the development of digital design on different FPGA technologies. He has considerable experience in LabVIEW.

Luca Fanucci received the Laurea and the Ph.D. degrees in Electronic Engineering from University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with the European Space Agency - ESTEC, Noordwijk (NL), as research fellow. From 1996 to 2004 he was a senior researcher of the Italian National Research Council in Pisa. Since 2004, he has been a professor of Electronics at the Department of Information Engineering, first as associate professor and then as full professor. His research interests include several aspects of design technologies for integrated circuits and electronic systems, with emphasis on system-level design, hardware/software co-design and sensor conditioning and data fusion. The main application areas are telecommunications, earth and space vehicles, medical systems and technological aids for disabled and elderly people. He is co-author of over 400 international journal and conference papers and co-inventor of more than 40 national and international patents or patents pending. He served in several technical programme committees of international conferences. He was Program Chair of DSD 2008 and DATE 2014 and General Chair of DATE 2016 and HiPEAC 2020. He is a member of the editorial board of IOS Press Technology and

Disability Journal. He is a Fellow of the Institute of Electrical and Electronic Engineers and a DATE Fellow.