Chapter1: Overview of Parasitic Substrate Coupling.- Chapter2: Design Challenges in High Voltage ICs.- Chapter3: Substrate Modeling with Parasitic Transistors.- Chapter4: TCAD Validation of the Model.- Chapter5: Extraction Tool for the Substrate Network.- Chapter6: Parasitic Bipolar Transistors in Benchmark Structures.- Chapter7: Substrate Coupling Analysis and Evaluation of Protection Strategies.
About the Author: Pietro Buccella is a postdoctoral researcher at EPFL in Lausanne, Switzerland. He received the Ph.D. degree in microsystems and microelectronics from EPFL, Switzerland ('16), the M.Sc. degree in electronic engineering from the Polytechnic University of Turin, Italy ('05). From 2005 to 2010, he was an analog IC design engineer at Microchip Technology Switzerland working in the field of sensor interface, high-voltage and power management CMOS integrated circuit design. From 2010 to 2012, he was a security engineer at Kudelski Group, testing the hardware security of microcontroller and smartcard chips. His main research interests include sensor interface, power management and mixed-signal HV IC design.
Camillo Stefanucci is an affiliated research scientist at the École Polytechnique Fédérale de Lausanne (EPFL, Switzerland). He received the Ph.D. degree in Microelectronics from EPFL, Switzerland ('16), the M.Sc. degree in electronic engineering from the Polytechnic University of Milan, Italy ('12) and the joined M.Sc. degree in Nanotechnologies from the Polytechnic University of Turin, Italy and the Institut National Polytechnique de Grenoble, France ('11). He has experience as analog IC designer at the Swiss Center of Microelectronics (CSEM) and ams AG where he develops industrial ASICs. His research and technical interests include latch-up modeling, power management circuits, HV analog design and data converters.
Maher Kayal received M.S. and Ph.D degrees in electrical engineering from the Ecole Polytechnique Fédérale de Lausanne (EPFL, Switzerland) in 1983 and 1989 respectively. He has been with the Electronics laboratories of the Ecole Polytechnique Fédérale de Lausanne (EPFL, Switzerland) since 1990, where he is currently a professor and director of the "Energy Management and Sustainability" section. He has published many scientific papers, coauthor of three text books dedicated to mixed-mode CMOS design and he holds eleven patents. His technical contributions have been in the area of analog and Mixed-signal circuits design including highly linear and tunable sensors microsystems, signal processing and green energy management.
Jean-Michel Sallese is a Senior Scientist at the Ecole Polytechnique Fédérale de Lausanne (Switzerland). His research is oriented towards analytical modeling of multigate semiconductor field effect transistors, modeling minority carrier propagation in semiconductors, simulation of high energy radiation damages in integrated circuits and novel concepts for Ultra High Fluence and Dose Radiation Sensors.
