The research community lacks both the capability to explain the effectiveness of existing techniques and the metrics to predict the security properties and vulnerabilities of the next generation of nano-devices and systems. This book provides in-depth viewpoints on security issues and explains how nano devices and their unique properties can address the opportunities and challenges of the security community, manufacturers, system integrators, and end users. This book elevates security as a fundamental design parameter, transforming the way new nano-devices are developed. Part 1 focuses on nano devices and building security primitives. Part 2 focuses on emerging technologies and integrations.
About the Author:

Mark M. Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Professor in Cybersecurity at the Department of Electrical and Computer Engineering, the University of Florida. His current research projects include: hardware security and trust, electronics supply chain security, counterfeit IC detection and prevention, and reliable and testable VLSI design. Prof. Tehranipoor has published over 300 journal articles and refereed conference papers and has given more than 150 invited talks and keynote addresses since 2006. In addition, he has 3 patents, and has published 6 books and 11 book chapters. His projects are sponsored by both the industry (Semiconductor Research Corporation [SRC], Texas Instruments, Freescale, Comcast, Honeywell, LSI, Mentor Graphics, Juniper, R3Logic, Cisco, Qualcomm, MediaTeck, etc.) and the U.S. Government (NSF, ARO, MDA, DOD, AFOSR, DOE, etc.).
He is a recipient of 12 best paper awards and nominations, the 2009 NSF CAREER award, the 2014 MURI award, the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2010 and 2016 IEEE TTTC/CS Most Successful Technical Event for co-founding and chairing HOST Symposium, the 2009 and 2014 UConn ECE Research Excellence Award, and the 2012 UConn SOE Outstanding Faculty Advisor Award.
He serves on the program committee of more than a dozen leading conferences and workshops. Prof. Tehranipoor served as the guest editor for JETTA, IEEE Design and Test of Computers, and IEEE Computer Society Computing Now. He served as Program Chair of the 2007 IEEE Defect-Based Testing (DBT) workshop, Program Chair of the 2008 IEEE Defect and Data Driven Testing (D3T) workshop, Co-program Chair of the 2008 International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), General Chair for D3T-2009 and DFTS-2009, and Vice-general Chair for NATW-2011.
He co-founded a new symposium called IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (http: //www.hostsymposium.org/) and served as HOST-2008 and HOST-2009 General Chair and continue to serve as Chair of the Steering Committee for HOST. He also co-founded IEEE Asian-HOST (http: //asianhost.org/). Further, he co-founded Journal on Hardware and Systems Security (HaSS) (http: //www.editorialmanager.com/hass). He is also a co-founder of Trust-Hub (http: //www.trust-hub.org/). He served as associate Editor-in-Chief (EIC) for IEEE Design and Test of Computers from 2012-2014. He is currently serving as an Associate Editor for IEEE Design and Test of Computers, an Associate Editor for JETTA, an Associate Editor for Journal of Low Power Electronics (JOLPE), an Associate Editor for ACM Transactions for Design Automation of Electronic Systems (TODAES). He has served as an IEEE Distinguished Speaker and an ACM Distinguished Speaker from 2010-2013.
Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Prof. Tehranipoor is a Senior Member of the IEEE, Golden Core Member of IEEE Computer Society, and Member of ACM and ACM SIGDA. He is also a member of Connecticut Academy of Science and Engineering (CASE).

Swarup Bhunia earned his BE (Hons.) from Jadavpur University, Kolkata, India, MTech from the Indian Institute of Technology (IIT), Kharagpur, and PhD from Purdue University, IN, USA. Currently, Dr. Bhunia is a professor in the University of Florida, FL, USA. Earlier he was appointed as the T. and A. Schroeder associate professor of Electrical Engineering and Computer Science at Case Western Reserve University, Cleveland, Ohio, USA. He has over ten years of research and development experience with over 200 publications in peer-reviewed journals and premier conferences. His research interests include hardware security and trust, adaptive nanocomputing and novel test methodologies. Dr. Bhunia received IBM Faculty Award (2013), National Science Foundation career development award (2011), Semiconductor Research Corporation Inventor Recognition Award (2009), and SRC technical excellence award (2005), and several best paper awards/nominations. He has been serving as an associate editor of IEEE Transactions on CAD, IEEE Transactions on Multi-Scale Computing Systems, ACM Journal of Emerging Technologies, and Journal of Low Power Electronics; served as guest editor of IEEE Design & Test of Computers (2010, 2013) and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2014). He has served as co-program chair of IEEE IMS3TW 2011, IEEE NANOARCH 2013, IEEE VDAT 2014, and IEEE HOST 2015, and in the program committee of many IEEE/ACM conferences. He is a senior member of IEEE.

Domenic Forte earned his BS degree in Electrical Engineering from Manhattan College, Riverdale, New York, in 2006, and the MS and PhD degrees in Electrical Engineering from the University of Maryland, College Park, Maryland, in 2010 and 2013, respectively. He is currently an Assistant Professor with the Electrical and Computer Engineering Department, University of Florida, Gainesville, Florida, where he has been since July 2015. Previously, he was an Assistant Professor of the Department of Electrical and Computer Engineering, University of Connecticut. His research is primarily focused on the domain of hardware security and includes investigation of hardware security primitives, hardware Trojan detection and prevention, security of the electronics supply chain, and anti-reverse engineering. Dr. Forte has received several research and teaching honors including 2016 Army Research Office Young Investigator award, 2008 George Corcoran Outstanding Teaching award, Hardware Oriented Security and Trust (HOST) 2016 best paper award, HOST 2015 best paper award, and Design Automation Conference (DAC) 2012 best paper nomination. He is an Associate Editor of Springer Journal of Hardware and System Security (HaSS), a Guest Editor of the IEEE Computer 2016 Special Issue on "Supply Chain Security for Cyber-Infrastructure," and in the program committee of many IEEE/ACM conferences. Dr. Forte is also a co-author of the book "Counterfeit Integrated Circuits- Detection and Avoidance."

Garrett S. Rose earned his BS degree in computer engineering from Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg, in 2001 and his MS and PhD degrees in electrical engineering from the University of Virginia, Charlottesville, in 2003 and 2006, respectively. Presently, he is an Associate Professor in the Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville where his work is focused on research in the areas of nanoelectronic circuit design, neuromorphic computing and hardware security. Prior to that, from June 2011 to July 2014, he was with the Air Force Research Laboratory, Information Directorate, Rome, NY. From August 2006 to May 2011, he was an Assistant Professor in the Department of Electrical and Computer Engineering at the Polytechnic Institute of New York University, Brooklyn, NY. From May 2004 to August 2005 he was with the MITRE Corporation, McLean, VA, involved in the design and simulation of nanoscale circuits and systems. His research interests include low-power circuits, system-on-chip design, trusted hardware, and developing VLSI design methodologies for novel nanoelectronic technologies. Dr. Rose is a member of the Association of Computing Machinery, IEEE Circuits and Systems Society and IEEE Computer Society. He serves and has served on Technical Program Committees for several IEEE conferences (including ISCAS, GLSVLSI, NANOARCH) and workshops in the area of VLSI design. In 2010, he was a guest editor for a special issue of the ACM Journal of Emerging Technologies in Computing Systems that presented key papers from the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH'09). Since April 2014 he is an associate editor for IEEE Transactions on Nanotechnology.