1. Introduction to FPGA design
a. Xilinx FPGA architecture and design flow
b. Altera FPGA architecture and design flow
c. SOC design and flow and use of HDL
2. Introduction to HDL
a. VHDL Language and applications
b. Verilog Evolution and practical applications
c. SystemVerilog and use for design
d. SystemVerilog and use for verification
3. Introduction to SystemVerilog
i. Data Types
ii. Programming model
iii. Parameterized model
iv. Examples
4. Programming using SystemVerilog
a. Operators
b. Loops
c. Task and functions
d. Procedural blocks
e. Decision control statements
f. Casting using SystemVerilog
5. Combinational design using SystemVerilog
a. Adders
b. Subtractors
c. Multipliers
d. Dividers
e. MUX
f. Demux
g. Decoder
h. Encoder 6. Sequential design using SystemVerilog
a. Latches
b. Flip-flops
c. Counters
i. BCD
ii. Binary
iii. Gray
iv. Johnson
v. Ring
d. Shift Registers
i. SISO
ii. PIPO
iii. SIPO
iv. PISO
7. RTL design using SystemVerilog
a. Synthesizable systemverilog constructs
b. Interfaces c. Netlist
d. Synthesis using SystemVerilog
e. Complex Designs using SystemVerilog
i. ALU design
ii. Parity generators
iii. Processor core logic design
f. FSM Using SystemVerilog
i. Moore machines
ii. Mealy machines
8. Verification using SystemVerilog
a. Verification architecture
b. Verification planning
c. Verification Constructs
d. Coverage goals
e. Case study
9. Design Implementation using FPGA
a. 8-bit Processor design using SystemVerilog
i. Implementation using FPGA
ii. Design verification
iii. System Testing
Appendix
About the Author: Vaibbhav Taraate is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.
