Chapter 1 - Research and Development History of Three Dimensional (3D) Integration Technology 1.1 Introduction 1.1.1 The International Technology Roadmap for Semiconductors 1.1.2 Three-dimensional Integration Technology 1.2 Motivation for 3D Integration Technology y 1.3 Research and Development History of 3D Integration Technology R&D History of 3D Packaging Technology 1.3.1 3D Packaging Technology 1.3.2 Origin of the TSV Concept 1.3.3 Research and Development History of 3D Technology in Organizations 1.3.3.1 Japan 1.3.3.2 Japanese 3D Integration Technology Research and Development Project (Dream Chip) 1.3.3.3 USA 1.3.3.4 Europe 1.3.3.5 Asia 1.3.3.6 International 1.4 Research and Development History of 3D Integration Technology for Applications 1.4.1 CMOS Image Sensor and MEMS 1.4.2 DRAM 1.4.3 2.5D with Interposer 1.4.4 Others Chapter 2- Recent Research and Development Activities of Three Dimensional (3D) Integration Technology 2.1 Recent Announcement of Research and Development Activities 2.2 Dynamic Random-Access Memory (DRAM) 2.2.1 Through-Silicon Via (TSV) Technology for DRAM 2.2.2 Wide I/O and Wide I/O2 Mobile DRAM 2.3 Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) DRAM 2.3.1 Hybrid Memory Cube (HMC)High Bandwidth Memory (HBM) DRAM 2.3.2 High Bandwidth Memory (HBM) DRAM 2.4 FPGA and 2.5D 2.5 Others 2.6 New Energy and Industrial Technology Development Organization (NEDO) Japan 2.6.1 Next Generation "Smart Device" Project 2.6.2 Background, Purpose and Target of "Smart Device" Project Chapter 3- TSV Processes 3.1 Deep Silicon Etching by Bosch process 3.1.1 Introduction 3.1.2 Basic characteristics of the Bosch process 3.1.3 Bosch Etching Equipment for TSV 3.1.4 Conclusions 3.2 High Rate Silicon-Via Etching and Basics of Sidewall Etch Reaction by Steady-State Etch Process 3.2.1 Introduction 3.2.2 MERIE Process for TSV Application 3.2.2.1 Effect of RF Frequency 3.2.2.2 Effect of Pressure 3.2.2.3 Effect of Oxygen Addition 3.2.3 Investigation of Sidewall Etch Reaction Induced by SF6/O2 Plasma 3.2.3.1 Effect of Oxygen Addition 3.2.3.2 Effect of Temperature 3.2.3.3 Effect of SiF4 Addition 3.2.4 Conclusion 3.3 Low Temperature CVD Technology 3.3.1 Introduction 3.3.2 Cathode-Coupled PECVD (LS-CVD) 3.3.3 Low Temperature SiO2 Deposition 3.3.3.1 Wafer Temperature During Low Temperature Deposition 3.3.3.2 Step Coverage in Si Via Holes 3.3.3.3 Electrical Characteristics of SiO2 Film Deposited at Low Temperature 3.3.3.4 Stress Control of SiO2 Film Deposited Using LS-CVD 3.3.4 Conclusion 3.4 Electrodeposition for Via-Filling 3.4.1 Cu+ Ion as an Accelerant Additive of Copper Electrodeposition 3.4.2 Relation between via Filling and Cu+ Ion by Periodical Reverse Current Waveform 3.4.3 Simulation of Cu+ Ion Distribution inside the Via 3.4.4 High Speed via Filling Electrodeposition by Other Organizations 3.4.5 Reduction of Thermal Expansion Coefficient of Electrodeposited Copper for TSV by Additive Chapter 4 - Wafer Handling and Thinning Processes 4.1 Wafer Thinning Solution for TSV Devices 4.1.1 Introduction 4.1.2 General Thinning 4.1.3 Wafer Thinning for TSV devices 4.1.4 TTV control 4.1.5 Summary 4.2 A Novel Via Middle TSV Thinning Technology by Si/Cu Grinding and CMP 4.2.1 Introduction 4.2.2 Methods 4.2.3 Results and Discussion 4.2.3.1 Si/Cu Same Rate CMP (1st CMP) 4.2.3.2 TSV Protrusion CMP (2nd CMP) 4.2.3.3 Post CMP Cleaning after 2nd CMP 4.2.4 Conclusion 4.3 Temporally Bonding 4.3.1 Background 4.3.2 The 3MTM Temporary Bonding Materials 4.3.3 The 3MTM Temporary Adhesive 4.3.4 Laser Absorbing Layer 4.3.5 The Next Steps 4.4 Temporary Bonding and Debonding for Through-Silicon Via (TSV) Processing 4.4.1 Introduction 4.4.2 Temporary Bonding and Debonding Process 4.4.3 Debonding Method 4.4.4 Functions and Performance Requirements for Temporary Bonding Device 4.4.5 Ability and Performance Requirements for Debonding Devices 4.4.6 Tokyo Electron's Temporary Bonder and Debonder Device Concept and Lineup 4.4.7 Future Outlook Chapter
About the Author:

Kazuo Kondo is Professor at Department of Chemical engineering, Osaka Prefecture University. He took his PhD in Chemical Engineering at the University of Illinois in 1981. He has worked for Sumitomo Metal Industries, Hokkaido University and Okayama University. He has 200 research publications and 100 patents. His major research is Copper Electrodeposition for TSV. His research extends in various fields not only in electrodeposition, but also in battery and CVD. He is member of Electrochemical Society, IEEE, Society of Chemical engineering Japan, Japanese Institute of Electronics Packaging, Surface Finishing Society of Japan, Materia Japan, Electrochemistry Japan and Japanese Society of Applied Physics.

Morihiro Kada is the invited researcher of The National Institute of Advanced Industrial Science and Technology (AIST) and the part-time researcher of Osaka Prefecture University. Prior to joining to AIST and the university he was the consultant of Association of Super-Advanced Electronics Technologies (ASET). Since April 2007 he has been heading the Japanese national R&D project on 3D-Integration technology as the Project in ASET. Before joining to ASET, he had been the General Manager of the Advanced Packaging Development Department in Sharp Corporation. He has more than forty years experience in semiconductor packaging engineering, with major emphasis on developing chip scale, chip stack package and Three Dimensional-System in Package (3D-SiP) as the pioneer of 3D-Integration technology in the world.

Kenji Takahashi is a Chief Specialist at Memory Packaging Development Department, Memory Division, Semiconductor & Strage Company, Toshiba Corporation. He received a M.E. Degree of from Chemical Engineering at the University of Tokyo in 1984 and Ph.D. from Information Science and Electrical Engineering at Kyushu University in 2010. His major research and development is focused on semiconductor packaging and